Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
| Autor: | Shih-Chieh Chang, Yu-Guang Chen, Yiyu Shi, Wing-Kai Hon, Wan-Yu Wen |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Engineering
Through-silicon via business.industry Heuristic Reliability (computer networking) Fault tolerance Hardware_PERFORMANCEANDRELIABILITY Computer Graphics and Computer-Aided Design Reliability engineering Spare part Overhead (computing) Electrical and Electronic Engineering Routing (electronic design automation) business Heuristics Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34:577-588 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2014.2385759 |
| Popis: | In 3-D integrated circuits, through silicon via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment, or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as a constrained graph decomposition problem. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 61%, compared with a seemingly more intuitive nearest-neighbor-based heuristic. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|