| Autor: |
Thomas A. Wassick, Paul S. Andry, Cyril Cabral, Russell Kastberg, Shidong Li, Mukta G. Farooq, Katsuyuki Sakuma, D. McHerron, Rajalingam Sankeerth |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
2021 IEEE 71st Electronic Components and Technology Conference (ECTC). |
| Popis: |
In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has been joined to a mixed pitch ( $5\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) high density interconnect laminate. By using the 3D-DSS process with thermal compression bonding, the thin bottom die with the TSVs can be bonded to a thick top die by being held flat with a silicon vacuum stage. This study used a semiconductor die that consisted of mixed pitch ( $55\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) Cu pillars with a SnAg solder cap. The dimension of the high-density laminate was $35 \text{mm} \times 35\ \text{mm}$ and it had thin film high density layers on standard build up layer. The thin film layers are directly integrated to one side of a conventional substrate. A major challenge for this technology lies in the interconnection reliability. To address that, sub-modeling of the interconnects was performed. The stresses in the solder micro-bump, back-end-of-the-line (BEOL) and the vias in the wiring level is presented. A selective cross-sectional analysis was used to study the geometry of the micro-bump connections after forming the 3D die stack on the advanced ground rule laminate. The analysis confirmed that mixed pitch solder joints along the perimeter of chips were joined with full wetting and no bridging. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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