Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits
| Autor: | M.A. Alam, Bipul C. Paul, Kunhyuk Kang, H. Kufluoglu, Kaushik Roy |
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| Rok vydání: | 2007 |
| Předmět: |
Digital electronics
Negative-bias temperature instability Computer science business.industry Transistor Hardware_PERFORMANCEANDRELIABILITY Computer Graphics and Computer-Aided Design law.invention Threshold voltage Reliability (semiconductor) Nanoelectronics CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Software Hardware_LOGICDESIGN Degradation (telecommunications) Electronic circuit |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:743-751 |
| ISSN: | 0278-0070 |
| DOI: | 10.1109/tcad.2006.884870 |
| Popis: | Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years |
| Databáze: | OpenAIRE |
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