A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices

Autor:	Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee, Chi-Heng Yang
Rok vydání:	2011
Předmět:	Chien search CMOS Gate count Computer science Logic gate Data_CODINGANDINFORMATIONTHEORY Parallel computing Electrical and Electronic Engineering Error detection and correction Flash memory Decoding methods BCH code
Zdroj:	IEEE Transactions on Circuits and Systems II: Express Briefs. 58:682-686
ISSN:	1558-3791 1549-7747
DOI:	10.1109/tcsii.2011.2161704
Popis:	According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0bd27dad75f5dd18d1a955fccc94dae4 https://doi.org/10.1109/tcsii.2011.2161704 Zobrazit plný text záznamu