Characteristics and reliability of metal–oxide–semiconductor transistors with various depths of plasma-induced Si recess structure
| Autor: | Chia Yu Kao, Hao Tang Hsu, Jone F. Chen, Yen Lin Tsai, Chun Yen Chen, Hann Ping Hwang |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science Physics and Astronomy (miscellaneous) business.industry 020208 electrical & electronic engineering Transistor General Engineering General Physics and Astronomy 02 engineering and technology Plasma Substrate (electronics) 01 natural sciences law.invention Metal Reliability (semiconductor) Oxide semiconductor law Electric field visual_art 0103 physical sciences 0202 electrical engineering electronic engineering information engineering visual_art.visual_art_medium Optoelectronics Breakdown voltage business |
| Zdroj: | Japanese Journal of Applied Physics. 57:04FD01 |
| ISSN: | 1347-4065 0021-4922 |
| DOI: | 10.7567/jjap.57.04fd01 |
| Popis: | Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology. |
| Databáze: | OpenAIRE |
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