A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μm high-density BiCMOS SRAM technology

Autor:	J.D. Hayden, R.C. Taft
Rok vydání:	1995
Předmět:	Materials science business.industry Bipolar junction transistor Electrical engineering BiCMOS Current source Electronic Optical and Magnetic Materials Logic gate Current-mode logic Static random-access memory Electrical and Electronic Engineering business Scaling Voltage
Zdroj:	IEEE Electron Device Letters. 16:88-90
ISSN:	1558-0563 0741-3106
Popis:	We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a /spl sim/30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 /spl mu/A switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0b64e334557e85d46fa7570ca870a459 https://doi.org/10.1109/55.363233 Zobrazit plný text záznamu