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Networks on Chip (NoC) have emerged as a promising interconnection technology for scalable many-core architectures. Proposed NoC-architectures and topologies often assume uniform distribution of traffic, where all tiles produce and consume the same amount of data. However, even in homogeneous many-core architectures the Network on Chip is used to access peripheral buses and memory controllers for off-chip memory access. These components can consume and generate a significant part of the overall traffic, thus having higher bandwidth requirements than processing tiles. In this work we propose High Bandwidth Routers replacing conventional routers within the NoC at the positions, where components with high bandwidth requirements are attached. A High Bandwidth Router design is proposed and investigated with respect to performance and implementation costs. The position of memory nodes within a tiled architecture is analyzed. The results show a significant improvement of throughput and reduction of latency for memory communication, with moderate additional implementation costs. |
