| Autor: |
Cangsang Zhao, Yong-Gee Ng, J. Kolonsek, Uddalak Bhattacharya, H.D. Varadarajan, N. Nintunze, K. Sarkez, M. Denham, Y. Lu |
| Rok vydání: |
1999 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 34:1564-1570 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.799864 |
| Popis: |
This 18 Mb pipeline-burst cache SRAM has 12.3 GB/s data transfer rate. The 14.3/spl times/14.6 mm/sup 2/ chip uses a 5.6 /spl mu/m/sup 2/ (2.22/spl times/2.52) 6-transistor cell and is fabricated on 0.18 /spl mu/m 6-metal-layer, 1.3-1.5 V CMOS. The paper shows the chip floor plan and array architecture. The chip is divided into four quadrants, each composed of 19 global subarrays, including one for redundancy. A data transfer rate of 1.54 Gb/s/pin on each I/O is achieved with a 770 MHz 50% duty cycle clock at 1.5 V, 25/spl deg/C. Data transition is on both clock edges using dual-edge-triggered flip-flops. With an 8 B I/O port (64-data and 8-parity pins), the chip has an aggregate bandwidth of 12.3 GB/s. A cycle on this SRAM actually refers to one half period (or a phase) of the clock. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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