Carrizo: A High Performance, Energy Efficient 28 nm APU
| Autor: | Russell Schreiber, Guhan Krishnan, Dave Johnson, Hugh McIntyre, Jim Farrell, David Akeson, Samuel D. Naffziger, Srikanth Arekapudi, Jonathan White, Benjamin Munger, Tom Burd, Kathryn Wilcox, Edward J. McLellan, Harry R. Fair, Sriram Sundaram |
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| Rok vydání: | 2016 |
| Předmět: |
Power management
Multi-core processor Engineering CPU cache business.industry 020208 electrical & electronic engineering Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 020202 computer hardware & architecture law.invention law Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering business Power density Efficient energy use Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:105-116 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | AMD's 6th generation “Carrizo” APU, targeted at 12–35 W mobile computing form factors, contains 3.1 billion transistors, occupies 250.04 mm $^{2}$ and is implemented in a 28 nm HKMG planar dual-oxide FET technology with 12 metal layers. The design achieves a 29% improvement in transistor density compared to the 5th generation “Kaveri” APU, also a 28 nm design, and implements several power management features resulting in area and power improvements similar to a technology shrink. Increased power density makes meeting the thermal limits required for reliability and power distribution to the APU's processors substantial design challenges. Pre-silicon thermal analysis is used to understand and take advantage of thermal gradients. Adaptive voltage-frequency scaling in the processor core as well as wordline and bitline assist techniques in the L2 cache enable lower minimum voltage requirements. |
| Databáze: | OpenAIRE |
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