IBM z13 circuit design and methodology
| Autor: | Charudhattan Nagarajan, Sridhar H. Rangarajan, Y.H. Chan, John Badar, Y.-H. Chan, M. Mayo, S. Carey, Matt Ziegler, L. Sigal, Thomas Strach, Christopher J. Berry, Niels Fricke, Gerald Strevig, Jose L. Neves, Frank Malgioglio, Dieter Wendel, Donald W. Plass, Ruchir Puri, John Isakson, A. Aipperspach, D. Malone, Robert M. Averill, James D. Warnock, Gerard M. Salem, Friedrich Schroeder, K. Lind, Howard H. Smith, Michael H. Wood, Jesse Surprise, Ricardo H. Nigaglioni, Guenter Mayer, D. Phan |
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| Rok vydání: | 2015 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
General Computer Science Computer science business.industry Circuit design Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Integrated circuit design Emitter-coupled logic eDRAM Chip law.invention Computer architecture law Hardware_INTEGRATEDCIRCUITS Physical design business Computer hardware Register-transfer level |
| Zdroj: | IBM Journal of Research and Development. 59:15:1-15:15 |
| ISSN: | 0018-8646 |
| Popis: | The two chips at the heart of the IBM z13™ system include a processor chip (referred to as the CP or Central Processor chip) and an L4 (Level 4) cache chip (referred to as the SC or System Controller chip), each 678 mm2 in area. The CP and SC chips were implemented with approximately 4 billion (4 × 109) and 7.1 billion transistors, respectively, in IBM's 22-nm SOI (silicon-on-insulator) technology, supporting eDRAM (embedded dynamic random access memory), and with up to 17 levels of metal available. In this paper, we discuss aspects of the circuit and physical design of these chips, including both digital logic and custom array implementation. In addition, we describe the design analysis methodology, along with some of the checks needed to ensure a robust, reliable, and high-frequency product. |
| Databáze: | OpenAIRE |
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