Notice of Violation of IEEE Publication Principles - Jitter analysis of a mixed PLL-DLL architecture
| Autor: | A.L. Scholtz, M. Sayfullah, B. Roland |
|---|---|
| Rok vydání: | 2008 |
| Předmět: |
Noise (signal processing)
Computer science Low-pass filter Hardware_PERFORMANCEANDRELIABILITY Transfer function Phase-locked loop Delay-locked loop Hardware_INTEGRATEDCIRCUITS Electronic engineering Architecture Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Phase frequency detector Hardware_LOGICDESIGN Jitter |
| Zdroj: | 2008 International Conference on Electrical and Computer Engineering. |
| Popis: | This paper presents the jitter analysis of a mixed mode phase locked loop (PLL) - delay locked loop (DLL) architecture. According to the jitter type, this model can be used as pure PLL or pure DLL or a mixed PLL-DLL. It is observed that mixed mode PLL-DLL architecture can combine the advantage from both PLL and DLL to reduce jitter. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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