Impact of stress-induced backflow on full-chip electromigration risk assessment
| Autor: | H. Haznedar, Chanhee Oh, Vladimir Zolotov, Rajendran Panda, Pon Sung Ku, M. Gall |
|---|---|
| Rok vydání: | 2006 |
| Předmět: |
Engineering
business.industry Linear system Topology (electrical circuits) Chip System of linear equations Topology Computer Graphics and Computer-Aided Design Electromigration Stress (mechanics) Electronic engineering Electrical and Electronic Engineering Hydrostatic stress business Software Backflow |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1038-1046 |
| ISSN: | 0278-0070 |
| DOI: | 10.1109/tcad.2005.855941 |
| Popis: | This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing high-performance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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