Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations
| Autor: | David Chinnery, Ankur Sharma, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Speedup
Computer science 02 engineering and technology Parallel computing RC time constant Directed acyclic graph Computer Graphics and Computer-Aided Design Capacitance 020202 computer hardware & architecture Reduction (complexity) symbols.namesake Tree traversal Lagrangian relaxation Logic gate 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Netlist symbols Electrical and Electronic Engineering Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:1456-1469 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2019.2915324 |
| Popis: | Accurate delay analysis with distributed RC delay can be computationally expensive, and can contribute the majority of the total runtime for gate sizers. Recent works have shown that Lagrangian relaxation (LR)-based gate sizers have produced designs with the lowest power on average. But they are also very slow due to a large number of expensive timing updates spread across several tens of iterations. In this paper, we develop an LR-based discrete gate sizer for fast timing and power reduction. Our gate sizer is multithreaded and is equipped with parallelization enabling techniques, namely mutual exclusion edge (MEE) assignment and directed acyclic graph (DAG)-based netlist traversal (DNT). MEEs are dummy edges assigned to improve load sharing among different threads. DNT facilitates simultaneous resizing of gates belonging to different topological levels. Our Lagrange multiplier update strategy enables rapid convergence of our timing and power recovery algorithms. To reduce the runtime of timing updates, we propose a simple and fast-to-compute effective capacitance model. We further propose mechanisms to calibrate timing models to improve their accuracy. By calibrating the internal timing models only twice, our proposed gate sizing flow facilitates extremely fast design optimization. We benchmark our gate sizer using the ISPD 2012 and 2013 gate sizing contest benchmark suites. Compared to the state-of-the-art gate sizer, our proposed gate sizer is on average $15\times $ faster and the optimized designs have 2.5% higher leakage power. Since we tradeoff timing accuracy for larger runtime speedup, our optimized designs have small timing violations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|