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A network partitioning tool, named Autonomous, is presented for partitioning digital combinational portions of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. A built-in self-test (BIST) design generators, named BISTSYN has been developed and implemented to facilitate the BIST design with this partitioning methodology. The experimental results show that Autonomous, when used with BISTSYN on a set of benchmark examples, is feasible for very large designs, and the number of undetected faults is significantly reduced after the circuit is partitioned. > |