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This work proposes a memory optimization technique for embedded Multi-Layer Perceptron (MLP) Artificial Neural Networks (ANNs) applications in a Microcontroller (µC) device as implementation platform. This platform has an attached general-purpose processor as one if its peripheral device and, as usual for this kind of hardware, the memory size is significantly lower when compared to other devices in which ANNs are implemented. This work demonstrate that Harvard architecture µCS such as ATmega family of µCS, NXP's MK20DX128VLF5, ESPRESSIF's ESP8266, ESP32 and the family of PIC32 µCS ease the storage of synaptic weights in program memory in such a way that these weights can be read at run time, without continuously occupying the data memory (RAM). This enables the application of larger and more complex ANN architectures on these low-power, low-cost and low-memory devices. The implementation here presented was developed in a ATmega-2560 µC and the embedded MLP neural network was trained to classify the digits from 0 to 9 of the MNIST Dataset. |
