Implementation of cell array neuro-processor by using FPGA
| Autor: | N. Akita, K. Komoku, T. Morishita, I. Teramoto, Fumihiro Hatano |
|---|---|
| Rok vydání: | 2003 |
| Předmět: |
Hardware architecture
Adder Computer architecture Computer science Hardware description language VHDL Hardware_ARITHMETICANDLOGICSTRUCTURES ComputerSystemsOrganization_PROCESSORARCHITECTURES Field-programmable gate array computer Reconfigurable computing computer.programming_language Register-transfer level |
| Zdroj: | IJCNN |
| DOI: | 10.1109/ijcnn.1999.833454 |
| Popis: | We have been studying the neuro-processor that is reconfigured according to needs. We propose an architecture and examine the components of this processor. We implement this processor by using FPGAs. We design this processor by a hardware description language (HDL) and prepare the components to satisfy the architecture. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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