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Quad Flat No lead (QFN) is a common package, which widely uses in the semiconductor industry. It has high advantage of low cost, flexible size and footprint, good heat dissipation with ability to have die attach paddle (DAP) expose and lower electrical parasitic resistance. Power devices in QFN can provide a low electrical resistance (RDS(on)) solution compare with tradition Transistor Outline (TO) Package or small outline integrated circuit (SOIC) package. To continue to minimum the driver's electrical parasitic resistance is the key characteristic for current power MOSFET technology developments. Recently copper clip package plays a critical role in meeting the increasing requirement for lower resistance (RDS(on)) devices, higher power density and high frequency switching applications. However, copper clip package poses multiple packaging manufacturability and reliability challenges. Solder attach for MOSFET and copper clip is a complex process that will affect the package resistance performance. This paper manages all the knowledge of RDS(on) failure which related to packaging. The learning of this study can be established database and guideline for copper clip package from design to manufacturing readiness and will help to have correct design for manufacturability (DFM), identify high risk before fabrication and troubleshooting during production. |
