Low‐loss 7‐bit S‐band CMOS passive phase shifter with digital control
| Autor: | Shankar Kumar Selvaraja, Vijay Kumar, Madhava Kumar, G. Sai Saravanan, Divya Kumar Garg |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Frequency band Applied Mathematics 020208 electrical & electronic engineering 020206 networking & telecommunications Topology (electrical circuits) 02 engineering and technology Computer Science Applications Electronic Optical and Magnetic Materials Root mean square CMOS 0202 electrical engineering electronic engineering information engineering Electronic engineering Insertion loss Output impedance S band Electrical and Electronic Engineering Phase shift module |
| Zdroj: | International Journal of Circuit Theory and Applications. 47:542-548 |
| ISSN: | 1097-007X 0098-9886 |
| DOI: | 10.1002/cta.2600 |
| Popis: | This paper presents the design and implementation of a 7-bit S-band digital passive phase shifter using Complementary Metal-Oxide-Semiconductor (CMOS) 65-nm technology in 2.6- to 3.2-GHz frequency band. New switched delay network topology has been used for 5.625 degrees and 2.8 degrees, and modified switched filter topology has been used for implementation of other phase bits to achieve 7-bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7-bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0 degrees, average RMS amplitude error of less than 0.6 dB, input matching (S-11) better than -7.5 dB, and output matching (S-22) better than -14.5 dB across the target frequency band at 50 omega input/output impedance. |
| Databáze: | OpenAIRE |
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