A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
| Autor: | Ying-Hsi Lin, Alex Chun-Hsien Wu, Ke-Horng Chen, Yu-Huei Lee, Chao-Chang Chiu, Shih-Wei Wang, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai, Shen-Yu Peng |
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| Rok vydání: | 2013 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 48:1018-1030 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2013.2237991 |
| Popis: | A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm2 in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/μs as well as the improved MIPS performance by 5.6 times was achieved. |
| Databáze: | OpenAIRE |
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