Synthesis and exploration of clock spines
| Autor: | Youngchan Kim, Taewhan Kim |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Computer science
Computation 0211 other engineering and technologies 02 engineering and technology Parallel computing Clock skew Reverse Polish notation Slicing Floorplan 020202 computer hardware & architecture Hardware and Architecture ComputerSystemsOrganization_MISCELLANEOUS 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Network synthesis filters Software 021106 design practice & management Electronic circuit |
| Zdroj: | IET Computers & Digital Techniques. 12:241-248 |
| ISSN: | 1751-861X 1751-8601 |
| DOI: | 10.1049/iet-cdt.2017.0234 |
| Popis: | This study addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimisation (SFO) problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the SFO. As a result, the authors proposed synthesis algorithm can explore the diverse structures of the clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that the proposed algorithm is able to synthesise the clock spine networks with 38% reduced clock skew over the clock tree structures, even 11% reduced clock power. In addition, in comparison with the clock mesh structures, the proposed clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|
Plný text