A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS
| Autor: | Yung-Hui Chung, Song-You Shih |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Spurious-free dynamic range
business.industry Computer science 020208 electrical & electronic engineering Electrical engineering Linearity Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Capacitance law.invention Capacitor Bit (horse) Effective number of bits CMOS law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering business |
| Zdroj: | VLSI-DAT |
| Popis: | This paper presents a 10-bit 100-MS/s SAR ADC incorporating a capacitor-swapping technique. The proposed swapping technique effectively removes the major capacitor-DAC transition error, resulting in improved linearity, without needing large capacitor size. To maintain good production yield, a dual-reference C-DAC is proposed to avoid using a tiny unit capacitance. The ADC was implemented in a 90-nm CMOS technology. At 100-MS/s, it consumes 1.25 mW from a 1-V supply. The measured peak SNDR and SFDR are 55.4 and 68 dB, respectively. Its ENOB is 8.91 bits, equivalent to a peak FoM of 26 fJ/conversion-step. |
| Databáze: | OpenAIRE |
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