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The application of self-timed logic to the design of a pipelined, parallel multiplier for two's complement, fixed-point numbers is described. Self-timing is used so that temporal control is distributed over the elements that compose the system, allowing elements to interact locally to run at their optimum speed. The weighted summation of partial products is carried out using a carry-save array, with a last-stage carry-propagate adder to form the final product. With the provision for carry-completion detection, the carry-propagate addition can be completed in an average time that varies as log/sub 2/ n for an n-bit adder. > |
