Bit rate and protocol independent clock and data recovery

Autor:	B. Stilling
Rok vydání:	2000
Předmět:	business.industry Computer science Detector Synchronization Data recovery Phase-locked loop Frequency-locked loop Clock domain crossing Delay-locked loop Electronic engineering Independent clock Electrical and Electronic Engineering business CPU multiplier
Zdroj:	Electronics Letters. 36:824
ISSN:	0013-5194
Popis:	A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). This architecture guarantees reliable clock synchronisation of the input data with different line codes over a frequency range spanning multiple octaves.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0606156dd00f35cd8e5bd7d3203d7e6c https://doi.org/10.1049/el:20000603 Zobrazit plný text záznamu