Encryption Time Comparison of AES on FPGA and Computer
| Autor: | Tarık Yerlikaya, Yasin Akman |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
business.industry
Computer science Encryption software Advanced Encryption Standard AES implementations Encryption Embedded system AES instruction set Verilog Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Computer hardware Key size computer.programming_language |
| Zdroj: | Advances in Intelligent Systems and Computing ISBN: 9783319009506 |
| Popis: | Advanced Encryption Standard (AES), which is approved and published by Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. The AES algorithm can be programmed in software or hardware. This paper presents encryption time comparison of the AES algorithm on FPGA and computer. In the study, Verilog HDL and C programming language is used on the FPGA and computer, respectively. The AES algorithm with 128-bit input and key length 128-bit (AES-128) was simulated on Xilinx ISE Design Suite 13.3. It was observed that, the AES algorithm runs on the FPGA faster than on a computer. We measured the time of encryption on FPGA and computer. Encryption time is 390ns of AES on FPGA and 11 μs of AES on a computer. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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