Slotted vias for dual damascene interconnects in 1 Gb DRAMs

Autor:	Stefan J. Weber, M. Hug, F. Zach, R. G. Filippi, K.P. Muller, J. Gambino, R.F. Schnabel, J.F. Nuetzel, Carl J. Radens, R. Iggulden, G. Mueller, Gary B. Bronner, Chenting Lin, David M. Dobuzinsky, Gregory Costrini, Larry Clevenger
Rok vydání:	2003
Předmět:	Interconnection Engineering business.industry Copper interconnect Hardware_PERFORMANCEANDRELIABILITY Chip Electromigration Capacitance Electrical resistance and conductance Hardware_INTEGRATEDCIRCUITS Electronic engineering Microelectronics business Dram
Zdroj:	1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
Popis:	A novel interconnect scheme is presented which has been used to significantly reduce the chip size of an 1 Gb SDRAM chip. The key element is the use of slotted vias for low resistance horizontal interconnects. This allows us to combine low capacitance/high resistance lines with low resistance/high capacitance lines. The slotted vias are realized by a dual damascene integration scheme without adding an additional mask level or process cost, with excellent continuity yield and good electromigration performance.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::059d52162b0e450c972bc25a440790a5 https://doi.org/10.1109/vlsit.1999.799331 Zobrazit plný text záznamu