| Autor: |
MinJae Lee, Riko Radojcic, KeunSoo Kim, Sam Gu, David Jon Hiner, Michael G. Kelly, Seokgeun Ahn, Hwankyu Kim, DaeByoung Kang, Dong Wook Kim, Ron Huemoeller |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
2015 IEEE 65th Electronic Components and Technology Conference (ECTC). |
| DOI: |
10.1109/ectc.2015.7159565 |
| Popis: |
Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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