| Autor: |
Sandeep Dhariwal, Vijay Kumar Lamba, Ravi Trivedi, Pratik Ghosh |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
2018 International Conference on Intelligent Circuits and Systems (ICICS). |
| DOI: |
10.1109/icics.2018.00019 |
| Popis: |
An efficient Phase Locked Loop (PLL) circuit with lower error rate Phase Frequency Detector (PFD), lower area, lower phase noise active inductor based Voltage Controlled Oscillator (VCO) and lesser current mismatch Charge Pump (CP) and passive loop filter was designed for a frequency synthesizer used in standard ZigBee based applications. For 2.4 GHz Industrial Scientific and Medical(ISM) band a precise synthesizer the PLL must have a better lock range and faster acquisition which is achieved by optimally designing PFD. We proposed a NAND based PFD using dynamic CMOS True Single-Phase Clock (TSPC) technique. A new Gyrator-C based active inductor with Quality factor (Q) enhancement technique for the LC-VCO to replace the on-chip spiral inductors in previous designs was proposed. This improved the phase noise at VCO's output using circuit controlled inductance with added benefit of lesser chip area. We used a linearizing circuit to lower the VCO's gain in order to improve the tuning range. The analysis was carried out on 180nm and 90nm generic process design kit (gpdk) CMOS technology and simulations on Cadence design environment. For a 2.4 GHz PLL, designed and simulated results showed the power consumption of 0.3mW for PFD and 20mW from active inductor based VCO and a Phase Noise of -110dBc/Hz. A comparative result between existing design and modified circuit has been provided. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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