Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

Autor:	Yoshikazu Ohara, J-C Bea, Takafumi Fukushima, Yutaka S. Sato, Mitsumasa Koyanagi, Hideki Hashimoto, S. Watanabe, K. Kiyoyama, S. Konno, M. Murugesan, K-W Lee, Tetsu Tanaka, T. Kamada, A. Yabata
Rok vydání:	2012
Předmět:	Materials science business.industry Hardware_INTEGRATEDCIRCUITS Stacking Electronic engineering Optoelectronics Image processing Hardware_PERFORMANCEANDRELIABILITY Image sensor business Chip Characterization (materials science)
Zdroj:	2012 International Electron Devices Meeting.
Popis:	We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::0545ae3d8c1e5376e27b0679bb6d4c66 https://doi.org/10.1109/iedm.2012.6479156 Zobrazit plný text záznamu