Design of low power comparator-reduced hybrid ADC
| Autor: | Hasan Molaei, Khosrow Hajsadeghi, Ata Khorami |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Offset (computer science)
Comparator Computer science 020208 electrical & electronic engineering General Engineering 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Effective number of bits CMOS Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Voltage |
| Zdroj: | Microelectronics Journal. 79:79-90 |
| ISSN: | 0026-2692 |
| DOI: | 10.1016/j.mejo.2018.07.005 |
| Popis: | This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s and the 8bit ADC consumes 4.6 mW at the 80 MS∕s. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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