Performance innovation in the IBM zEnterprise 196 processor
| Autor: | D. F. Greiner, Marcel Mitran, Craig R. Walters, T. J. Slegel, Charles F. Webb |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Enterprise architecture framework
General Computer Science Cellular architecture Computer science Transaction processing Enterprise architecture computer.software_genre Service-oriented modeling Functional software architecture Computer architecture Applications architecture Operating system Reference architecture computer |
| Zdroj: | IBM Journal of Research and Development. 56:6:1-6:14 |
| ISSN: | 0018-8646 |
| DOI: | 10.1147/jrd.2011.2177906 |
| Popis: | The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on today's enterprise information technology systems, ranging from large data-intensive transaction processing workloads to central processing unit-intensive business applications. Each of these required innovations in the design of the hardware, software, and instruction-set architecture (ISA) with performance gains coming from several sources: the out-of-order microprocessor core design, the multilevel cache structure, new ISA facilities, and additional ISA extensions to enable efficient scaling of large multiprocessor operating system images. These enhancements were achieved through collaborative development among hardware, software, compiler, architecture, and performance analysis teams. This paper describes the performance contributions from these sources, with particular focus on the new architectural facilities. |
| Databáze: | OpenAIRE |
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