| Autor: |
S.A. Mahmoud, D.P. Noel, Tad Kwasniewski, W.P. Leblanc |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
VTC |
| DOI: |
10.1109/vetec.1994.345030 |
| Popis: |
32 kb/s adaptive differential pulse coded modulation (ADPCM) is a widely accepted high quality speech coding algorithm. Single chip devices exist for 32 kb/s ADPCM. This algorithm requires a relatively large bandwidth and does not perform exceptionally well in noisy wireless environments. The 16 kb/s low-delay code excited linear prediction (LD-CELP) coding algorithm does perform well in noisy environments and requires a reduced bandwidth. Through algorithm optimization and simulated verification of mixed analog and digital VLSI partitioning a single chip implementing the 16 kb/s LD-CELP voice coding algorithm will be possible. The performance of this coder chip will be comparable to the quality of 32 kb/s ADPCM. In this paper we propose the use of a link between Comdisco's SPW and Synopsis to determine the hardware related performance degradation and the technology/complexity related power dissipation and area parameters. It will both prove the concept of design and determine the VLSI implementation feasibility. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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