| Popis: |
As the embedded system design focus moving from computation-centric to communication-centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect components for multi/many core systems due to the scalability and high bandwidth. However, the NoCs design has reached the bottleneck in terms of power consumption, data communication latency and chip area nowadays. 3D chip technologies have been brought into the NoCs design field to reduce the communication cost but increase the performance. A comprehensive design platform - Generic Scalable Networks-on-Chip (GSNoC) will be demonstrated in this paper, which can handle the 3D NoCs design at different design levels (application, architecture and circuit). Application generator, NoCs design framework, comprehensive cycle accurate system simulator and an user-friendly Graphic User Interface (GUI) have been developed in the platform. The entire platform is programmed in C++ and the hardware simulation part is programmed in SystemC. |
