| Autor: |
Sudha R. Karbari, Krishna B. Pandit |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
Lecture Notes in Electrical Engineering ISBN: 9789811602740 |
| DOI: |
10.1007/978-981-16-0275-7_51 |
| Popis: |
As the technology nodes are getting smaller and smaller the design of a SoC is becoming more complex day by day. Modern day SoCs are a collection of individual intellectual properties [IP]. Each IP has its own clocking regime and each clock belongs to the separate clock domains. This leads to the challenge in design and verification of SoCs. Designing of the SoCs involves proper synchronization schemes to be employed to synchronize signals crossing clock domains. The functional verification of SoCs is becoming more and more difficult due to the data transferred between individual IP modules. When data transfers between two IPs the data crosses clock domains leading to clock domain crossing [CDC]. For a SoC to be free of all CDC errors, verification is paramount along with meeting the timing requirements. The present work focuses on reduction of waivers and improving the QoR and the coverage of the design. This work also focuses on the verification of functionality of the synchronizers by simulation and assertion-based verification. Then finally to close the gap from verification to sign-off, the assertions are converted to equivalent timing checks and are validated through timing analysis. The results show that the methodology shows a reduction of waivers by 45% and improved the design coverage to 93%. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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