| Autor: |
Terada Yasukazu, Naoaki Yamanaka, Y. Yamamoto, Hiroshi Miyanaga, Y. Kobayashi |
| Rok vydání: |
1986 |
| Předmět: |
|
| Zdroj: |
IEEE Transactions on Communications. 34:953-955 |
| ISSN: |
0096-2244 |
| DOI: |
10.1109/tcom.1986.1096640 |
| Popis: |
A novel concept and structure for a high-speed time division switch operating in the gigabit/second range are presented. The basic concept is to use the high-speed memory in the time switch effectively by means of a slow writing/fast reading method. N numbers of speech data are written in parallel during N clock times and read serially during one clock time for one switched datum. By using the concept and high-speed memories that we have, a data switching system which approaches the memory and read cycle limit can be realized with a proper time margin. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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