A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration
| Autor: | Jin-Woo Kim, Russell P. Kraft, John F. McDonald, Aamir Zia, Michael Chu, Philip Jacob |
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| Rok vydání: | 2010 |
| Předmět: |
Reduced instruction set computing
Computer science Cache coloring CPU cache Pipeline burst cache Cache pollution Non-uniform memory access Write-once Hardware_INTEGRATEDCIRCUITS Static random-access memory Electrical and Electronic Engineering Latency (engineering) Direct memory access Multi-core processor Hardware_MEMORYSTRUCTURES business.industry Cache-only memory architecture Memory bandwidth Smart Cache Hardware and Architecture Embedded system Page cache Cache business Software Computer hardware |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:967-977 |
| ISSN: | 1557-9999 1063-8210 |
| Popis: | Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output. |
| Databáze: | OpenAIRE |
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