Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um2
| Autor: | Koutaro Sho, Mikio Katsumata, Taiki Kimura, Shoji Mimotogi, Tatsuhiko Ema, Seiji Nagahara, Fumikatsu Uesawa, Makoto Tominaga, Hiroki Hane, Hiroharu Fujise, Atsushi Ikegami, Masafumi Asano, Hideki Kanai, M. Iwai |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Materials science
business.industry Computational lithography Extreme ultraviolet lithography Hardware_PERFORMANCEANDRELIABILITY law.invention CMOS law Hardware_INTEGRATEDCIRCUITS Optoelectronics Phase-shift mask Photolithography business Lithography Next-generation lithography Immersion lithography Hardware_LOGICDESIGN ComputingMethodologies_COMPUTERGRAPHICS |
| Zdroj: | SPIE Proceedings. |
| ISSN: | 0277-786X |
| DOI: | 10.1117/12.711049 |
| Popis: | Immersion lithography was applied to 45nm node logic and 0.25um 2 ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|