FPGA-Based Data Storage System on NAND Flash Memory in RAID 6 Architecture for In-Line Pipeline Inspection Gauges
| Autor: | Luciano Nava-Balanzar, A. Gomez-Hernandez, Hugo Jiménez-Hernández, Noé Amir Rodríguez-Olivares, J. A. Soto-Cajiga |
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| Rok vydání: | 2018 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
business.industry Computer science Nand flash memory RAID Byte NAND gate 020206 networking & telecommunications 02 engineering and technology 020202 computer hardware & architecture Theoretical Computer Science law.invention Computational Theory and Mathematics Hardware and Architecture law Computer data storage 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) Cache business Software Flash file system Computer hardware |
| Zdroj: | IEEE Transactions on Computers. 67:1046-1053 |
| ISSN: | 0018-9340 |
| DOI: | 10.1109/tc.2018.2794986 |
| Popis: | In this manuscript, we present a redundant data storage system based on NAND flash memory chips for in-line Pipeline Inspection Gauges (PIGs). The system is the next step for a technique that reduces data from 1,024 to 37 bytes by 80 transducers used for straight-beam ultrasonic inspection. Each inspection is costly, because PIGs check pipelines up to 100 Km, collecting data every 3 mm and reaching speeds of 2 m/s. These conditions require that the storage system must be redundant, and able to maintain a minimum data flow, thus avoiding bottlenecks. To achieve this, we analyzed the variables that influence the inspection process in real-time, and we structured our Flash Translation Layer (FTL) to eliminate the latencies generated by the computation of the Error Correcting Codes (ECC) and redundancy bytes. Our controller computes the ECC and redundancy bytes while it transfers the information to the cache register of the selected die in the memory chips. At the hardware level, we interleaved 8 NAND flash chips in a Redundant Array of Independent Disks (RAID) type-6 architecture. We tested the storage system considering the incorrect response of up to 2 chips and ensuring a throughput up to 7.28 MB/s. Finally, we expanded the analysis of the data flow, whereby this system is profitable for different pipeline diameters or compression techniques. |
| Databáze: | OpenAIRE |
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