Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier
| Autor: | Noureddine Chabini, Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Computer science
business.industry Decimal floating point Binary-coded decimal 02 engineering and technology Fixed point Decimal 020202 computer hardware & architecture Lookup table VHDL 0202 electrical engineering electronic engineering information engineering Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array computer Computer hardware computer.programming_language |
| Zdroj: | CCECE |
| DOI: | 10.1109/ccece.2017.7946692 |
| Popis: | This paper presents the design of pipelined IEEE 754-2008 decimal floating-point (DFP) multipliers targeting FPGAs. A key component of the architecture is the fixed-point multiplier function which impacts the overall performance and area utilization. In this paper, we propose a new method to realize this operation by carefully organizing the partial products and developing an algorithm for binary-decimal compression. The DFP multipliers with 5 to 12 pipeline stages are coded in VHDL and implemented on a Xilinx Virtex-5 FPGA. The overall design is compared with another approach based on fixed-point multipliers using a BCD-4221 compression technique. Using post layout extracted design data, our approach achieves a delay improvement in the range of 7.9% to 20.3% and an average LUT reduction of 5%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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