Performance Analysis of Low Power Bypassing-Based Multiplier

Autor:	Anupa. S. Kavale, Mamta Mahajan, Dinesh Rotake
Rok vydání:	2014
Předmět:	Forcing (recursion theory) Computer science Electronic engineering Multiplier (economics) Electronics Hardware_ARITHMETICANDLOGICSTRUCTURES Parallel array AND gate Dsp processor NOR gate
Zdroj:	IOSR journal of VLSI and Signal Processing. 4:53-58
ISSN:	2319-4200 2319-4197
DOI:	10.9790/4200-04415358
Popis:	In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power is to be achieved in changed partial products of column bypassing multiplier as compared to column bypassing multiplier by exchange NOR gates with AND gates in the conventional multiplier I.e. in the design of conventional multiplier rather than AND gate, NOR gate is employed victimization DeMorgan’s theorem. Compare with 32×32 bits typical (parallel array) multiplier and column bypassing multiplier, this planned system consume less power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::02114654ff5bbbeee87dfca5aeda9f76 https://doi.org/10.9790/4200-04415358 Zobrazit plný text záznamu