Low-Complexity LDPC Decoder for 5G URLLC
| Autor: | Jian-Cheng Liu, Chung-An Shen, Huan-Chun Wang, Jih-Wei Lee |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Virtex
business.industry Computer science 020206 networking & telecommunications 02 engineering and technology 020202 computer hardware & architecture Reduction (complexity) Data dependency 0202 electrical engineering electronic engineering information engineering Latency (engineering) Low-density parity-check code business Field-programmable gate array Throughput (business) Decoding methods Computer hardware |
| Zdroj: | 2018 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia). |
| DOI: | 10.1109/primeasia.2018.8597812 |
| Popis: | This paper proposes a low-complexity low-density parity-check (LDPC) decoder architecture for 5G ultra-reliable low latency communication (URLLC). In order to reduce the hardware utilization and the influence of data dependency problem. Proposed low-complexity decoder reduces the number of multi-size shift modules of the conventional single-layer decoder from two to one by improve the method in [15]. Due to the reduction of multi-size shift modules, we also construct new matrices that generate the shift value in proposed low-complexity decoder. Using the FPGA platform of Xilinx Virtex 7, experimental results show our proposed low-complexity decoder improves the resources utilization and throughput of conventional architectures. The improvement in percentage is about 20.1% for LUTs and 6.8% for throughput. The experimental result show that our method is more efficient than [15]. |
| Databáze: | OpenAIRE |
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