A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET

Autor:	Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor Mudge, Ronald Dreslinski, Hun-Seok Kim, David Blaauw
Rok vydání:	2022
Zdroj:	2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::01c5f79f97de21510570812957ecb2a1 https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830330 Zobrazit plný text záznamu