A System Verilog Approach for Verification of Memory Controller

Autor:	Gagana P, Mythili M, Kariyappa B S
Rok vydání:	2020
Předmět:	business.industry Computer science Embedded system Verilog business computer Memory controller computer.programming_language
Zdroj:	International Journal of Engineering Research and.
ISSN:	2278-0181
DOI:	10.17577/ijertv9is050876
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::01ac409373b8ff7a51c2f57f1841b037 https://doi.org/10.17577/ijertv9is050876 Zobrazit plný text záznamu