A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance
| Autor: | Xizhu Peng, He Tang, Haoyu Zhuang, Cao Qifu |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Physics
business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY law.invention Acceleration Capacitor Parasitic capacitance Sampling (signal processing) law Logic gate Hardware_INTEGRATEDCIRCUITS Node (circuits) Hardware_ARITHMETICANDLOGICSTRUCTURES business NMOS logic Hardware_LOGICDESIGN Voltage |
| Zdroj: | ISCAS |
| Popis: | This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstrapped switch, this design accelerates the rising speed of gate voltage through four novel techniques. First, an extra NMOS transistor is added to pull up the gate voltage by injecting extra charges into the gate node. Second, the parasitic capacitance at the gate node is reduced by simplifying the circuit structure, leading to a faster speed. Third, transmission gates are used to reduce the two delays to one delay. Fourth, the voltage stored on the capacitor is increased to slightly larger than V DD , which leads to a faster gate-voltage rising speed as well as a larger value of gate voltage (about V n +1.05 V DD ). The larger gate voltage also helps reduce the on-resistance of the bootstrapped switch, which is helpful for the high-speed sampling of ADCs. In a 40 nm CMOS process, post-layout simulation results show that the rising speed of gate voltage is increased by 3.3 times compared to the classic thin-oxide bootstrapped switch circuit. And the on-resistance of the bootstrapped switch is reduced by 2.2 times compared to the classic structure, due to the larger gate voltage value. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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