FPGA implementation of LDPC encoder with approximate lower triangular matrix

Autor:	Jue Hsuan Hsiao, Jheng Shyuan He, Yi Hua Chen
Rok vydání:	2012
Předmět:	Parity-check matrix Channel code Theoretical computer science Computer science Triangular matrix Data_CODINGANDINFORMATIONTHEORY Software-defined radio Low-density parity-check code Field-programmable gate array Encoder Computational science Sparse matrix
Zdroj:	The 1st IEEE Global Conference on Consumer Electronics 2012.
DOI:	10.1109/gcce.2012.6379546
Popis:	This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::018ff31d5dc60e58c377d996fe7a2b18 https://doi.org/10.1109/gcce.2012.6379546 Zobrazit plný text záznamu