A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS
| Autor: | Min-Shueh Yuan, Hung-Yi Kuo, Chung-Ting Lu, Chao-Chieh Li, Hsien-Yuan Liao, Mark Chen, Kenny Hsieh, Augusto Ronchini Ximenes, Robert Bogdan Staszewski, Chih-Hsien Chang, Tien-Chien Huang, Chia-Chun Liao, Tsung-Hsien Tsai |
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| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Electrical engineering Estimator 02 engineering and technology law.invention Phase-locked loop Capacitor CMOS law PLL multibit 0202 electrical engineering electronic engineering information engineering Electronic engineering Inverter Transformer business Jitter |
| Zdroj: | VLSI Circuits |
| DOI: | 10.1109/vlsic.2016.7573551 |
| Popis: | A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8–19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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