Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow
| Autor: | Dave Reid, D. Vanhaeren, Salvatore Maria Amoroso, Pieter Weckx, Liping Wang, Ben Kaczer, Binjie Cheng, Asen Asenov, Naoto Horiguchi, Marco Simicic, Jacopo Franco, Annelies Vanderheyden, Razaidi Hussin, Louis Gerrer, Jie Ding |
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| Rok vydání: | 2015 |
| Předmět: |
Engineering
business.industry Calibration (statistics) Transistor Semiconductor device modeling Hardware_PERFORMANCEANDRELIABILITY Semiconductor process simulation law.invention Computer Science::Hardware Architecture law MOSFET Hardware_INTEGRATEDCIRCUITS Electronic engineering business Technology CAD Cell aging Electronic circuit |
| Zdroj: | ESSDERC |
| DOI: | 10.1109/essderc.2015.7324758 |
| Popis: | This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time. |
| Databáze: | OpenAIRE |
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