| Autor: |
L. Pastel, Frank Ray Keyser, G. Richardson, C. LaMarche, R. Taylor, Allan Robert Bertolet, Brian A. Worth, Albert M. Chu, T. Harroun, John George Petrovick |
| Rok vydání: |
1990 |
| Předmět: |
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| Zdroj: |
1990 37th IEEE International Conference on Solid-State Circuits. |
| DOI: |
10.1109/isscc.1990.110142 |
| Popis: |
A 300 K-circuit ASIC (application-specific-integrated-circuit) family built in a 0.8- mu m four-level-metal single-poly CMOS process is discussed. Wafers consist of p/sup +/ substrate with a p-epitaxial layer and retrograde n-wells. Polysilicon and diffusions are silicided for low resistance. Nominal effective channel length is 0.45 mu m and gate oxides are 120 A. A local interconnect level enhances density. Metal levels 1, 2, and 3 have a contact pitch of 2.4 mu m; metal level 4 has a pitch of 4.8 mu m. All metal lines are aluminum with tungsten vias. Chips are organized as a sea of cells. The standard-cell library consists of 91 combinatorial and sequential elements, available in three performance levels to control delay over a wide range of loads. Three types of embedded array macros are available: fixed custom static random-access memories (SRAMs), growable SRAMs (GRAMs), and growable register arrays (GRAs). Up to 472 full-function signal I/Os are available per chip. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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