| Autor: |
Seong-Ho Lee, Hui Pan, Haitao Tong, Wei Zhang, Hamid Hatamkhani, Duke Tran, Magesh Valliappan, Ichiro Fujimori, Karo Khanoyan, Anthony Brewster, Mario Caresosa, Kambiz Vakilian |
| Rok vydání: |
2011 |
| Předmět: |
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| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc.2011.5746389 |
| Popis: |
It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forwarded or has small frequency offset [2, 3], due to the finite frequency and jitter tracking capability of the digitally controlled phase rotation. Recently, tracking range up to ±7800ppm has been reported [4] to extend the applications to the SATA/SAS interfaces that require 5000ppm spread spectrum clocking (SSC) to suppress electromagnetic emissions. To enable broad acceptance in high-speed applications, the digital CDRs must have much wider tracking range. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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