Cache Utilization as a Locality Metric - A Case Study on the Mantevo Suite
| Autor: | Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Patricia Grubel, Jeanine Cook |
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| Rok vydání: | 2016 |
| Předmět: |
Computer science
Cache coloring CPU cache Distributed computing Pipeline burst cache 02 engineering and technology Cache-oblivious algorithm Cache pollution Cache invalidation Write-once 0202 electrical engineering electronic engineering information engineering Locality of reference Cache hierarchy Cache algorithms Snoopy cache Hardware_MEMORYSTRUCTURES Adaptive replacement cache MESI protocol Locality MESIF protocol 020202 computer hardware & architecture Smart Cache Bus sniffing 020201 artificial intelligence & image processing Page cache Cache |
| Zdroj: | 2016 International Conference on Computational Science and Computational Intelligence (CSCI). |
| Popis: | Cache hierarchies have long been utilized to minimize the latency of main memory accesses by caching frequently used data closer to the processor. Significant research has been done to identify the most crucial metrics of cache performance. Though the majority of research focuses on measuring cache hit rates and data movement as the major cache performance metrics, cache utilization can be equally important. In this work, we present cache utilization performance metrics that provide insight into application behavior. We define cache utilization in two forms: 1) the fraction of data bytes in a cache line that are actually accessed at least once before eviction from cache and 2) the access frequency of data bytes in a cache line. We discuss the relationship between the utilization measurement and two important application properties: 1) spatial locality – the use of data located near data that has already been accessed, and 2) temporal locality – the reuse of data over time. In addition to measuring cache line utilization performance, we present conventional performance metrics as well to illustrate a holistic understanding of cache behavior. To facilitate this work, we build a memory simulator incorporated into the Structural Simulation Toolkit (SST). We measure and analyze the performance for several scientific mini-applications from the Mantevo suite [1]. This work justifies that caches are not necessarily the best onchip solution for all types of applications due to the fixed cache line size. |
| Databáze: | OpenAIRE |
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