A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS
| Autor: | Woosung Park, Jahoon Jin, Minsu Park, Sangdon Jung, Jung-Hoon Chun |
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| Rok vydání: | 2022 |
| Zdroj: | 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC). |
| Databáze: | OpenAIRE |
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